Modeling of two-phase microchannel heat sinks for VLSI chips

Abstract

Microchannel heat sinks with forced convective boiling can satisfy the increasing heat removal requirements of VLSI chips. But little is known about two-phase boiling flow in channels with cross-sectional dimensions below 100 /spl mu/m. This work develops and experimentally verifies microchannel simulations, which relate the temperature field to the applied power and flowrate. The simulations consider silicon conduction and assume an immediate transition to homogeneous misty flow, without the bubbly and plug-flow regimes in larger channels. Pressure drop and wall temperature predictions are consistent with data for a channel with cross-sectional dimensions of 50 /spl mu/m/spl times/70 /spl mu/m. The simulations explore the performance of a novel heat sink system with an electrokinetic pump for the liquid phase, which provides 1 atm and 15 ml/min. A temperature rise below 40 K is predicted for a 200 W heat sink for a 25 mm/spl times/25 mm chip.