Clocking and Cell Placement for QCA

Abstract

In this paper we propose a novel two-dimensional clocking and timing scheme for systems which permit a reduction in the longest line length in each clocking zone. The proposed clocking schemes utilize logic propagation techniques which have been developed for systolic arrays. Placement of QCA cells is modified to ensure correct signal generation and timing. The significant reduction in the longest line length permits a fast timing and efficient pipelining to occur, while guaranteeing kink-free behavior in switching.