Dual-loop DPLL gear-shifting algorithm for fast synchronization

Abstract

Since most digital phase-locked loops (DPLL's) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady state, the DPLL loop bandwidth should be adjusted accordingly. In this paper, three bandwidth adjusting (gear-shifting) algorithms are presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. These algorithms suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithms can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period.