RAPPID: an asynchronous instruction length decoder

TLDR

The study examines the benefits and risks of applying aggressive asynchronous design to Intel Architecture. RAPPID, a prototype IA32 instruction decoder, was built with self‑timed techniques. The fabricated 0.25 µm RAPPID chip achieved 2.5–4.5 instructions/ns, tripling throughput, halving latency and power, while matching the area of a 400 MHz clocked circuit, demonstrating significant performance gains with manageable risks.

Abstract

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.