FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks

Abstract

Reconfigurable architectures are important elements on the design of software radios. Nowadays, diverse platforms are being developed to support multiple tasks; these platforms are designed specially for the different layers of the OSI (Open System Interconnection) reference model. Specifically, the security architectures described in the MAC sublayer should be evaluated, which are based on cryptographic algorithms that require high computational costs. In this work, two proposed AES-CCM hardware architectures for the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards are implemented in diverse FPGA devices to examine implementation costs and performance evaluation. The results presented in this work will be used for designing and developing a reconfigurable platform with software-radio applications, which will include the high-performance AES-CCM hardware architectures meeting the specifications of the IEEE 802.11i-2004 and IEEE 802.16e-2005 standards.