The circuits and physical design of the synergistic processor element of a CELL processor

TLDR

The synergistic processor element is a 32‑bit, 4‑way SIMD dual‑issue core built with 20.9 million transistors in a 14.8 mm², 90 nm SOI die, using mostly CMOS static gates and dynamic circuits in 19 % of the non‑SRAM area, with ISA, microarchitecture, and physical design tightly integrated for compactness and power efficiency. The core operates correctly at 5.6 GHz with a 1.4 V supply and tolerates temperatures up to 56 °C.

Abstract

A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sub 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C.