A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)

Abstract

A global net-length distribution for three-dimensional system-on-a-chip architectures is derived to quantify the impact of the number of strata, or active layers, on the length of the long global interconnects. Model projections indicate a reduction in the global net length as the square root of the number of strata, thus enabling a significant reduction in chip footprint area, power dissipation, and global cycle time in comparison to a two-dimensional system-on-a-chip. Unlike its homogeneous counterpart, the vertical integration of a heterogeneous system is not limited by the density of interstratal interconnects. The size of the large megacells, especially memory, may restrict the effectiveness of a large number of strata.