IEEE Journal of Solid-State Circuits · 2008 · 38 citations · 31 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignLow-noise Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog-to-digital ConversionAnalog-to-digital Converter DesignCmos Analog Integrated CircuitsCmos ScalingDigital-to-analog Converter DesignPipelined Digital CircuitsPower ConsumptionPower Consumption Optimization
A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.
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Comparator-based switched-capacitor circuits for scaled CMOS technologies
T. Sepke, John Kenneth Fiorenza, C.G. Sodini et al. · 2006 · 241 citations
Engineering, Computer Engineering, Electrical Engineering +17