High performance half-micron PMOSFETs with 0.1um shallow P<sup>+</sup>N junction utilizing selective silicon growth and rapid thermal annealing

Abstract

High performance half-micron PMOSFETs with extremely shallow junction and low parasitic resistance have been realized utilizing selective silicon growth(SSG) with rapid thermal anneal(RTA) processing. In the technology, SSG greatly contributes to reduction of effective junction depth for MOSFETs because of raised source/drain(S/D) structures, and RTA can effectively reduce the junction depth, S/D resistance, and contact resistance due to its excellent activation characteristics of implanted ions and anneal-out of fluorine induced defects. By combining SSG with RTA, shallow P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> N junction of 0.1µm depth, sheet resistance of 56ohm/square, and contact resistance of 30ohms for 0.8µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> contact were achieved simultaneously. Moreover, this device structure can provide relaxed alignment tolerances as well as more reliable contact characteristics by avoiding aluminum spiking. The feasibility of the fabrication process and device structure has been demonstrated.