High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25- BiCMOS Process for RF-Power Applications

D. Muller, Alexandre Giry, F. Judong, C. Rossato, F. Blanchet, Bertrand Szelag, A. Monroy Aguirre, Raphaël Sommet, Denis Pache, O. Noblanc

IEEE Transactions on Electron Devices · 2007 · 37 citations · 8 references

Concepts

Abstract

The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> - and power performances while maintaining good dc characteristics

References

8