Publication | Closed Access
Architectural yield analysis of random defects in wafer scale integration
10
Citations
7
References
2003
Year
Unknown Venue
EngineeringSystem-level DesignComputer-aided DesignDefect ToleranceSocial SciencesPhysical Design (Electronics)Reliability EngineeringWafer Scale ProcessingAdvanced Packaging (Semiconductors)Yield ManagementYield OptimizationTopological YieldYield EngineeringElectronic PackagingYield ConceptsElectrical EngineeringDesignComputer EngineeringYield (Engineering)MicroelectronicsArchitectural DesignChip-scale PackageArchitectural Yield AnalysisNew Models
Wafer-scale integration yield concepts are examined. New models of yield are defined and their utility is shown by analyzing the architectural and topological yield of some regular structures. Yield concepts are reviewed, the idea of architectural yield is defined, a mathematical framework for studying such yield is established, and assumptions are discussed. These are applied to architectural goals involving binary tree structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
| Year | Citations | |
|---|---|---|
Page 1
Page 1