An SEU-hardened CMOS data latch design

Abstract

A single-event-upset hardened CMOS data latch design is described. The hardness is achieved by virtue of the design; thus no fabrication process or design ground-rule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests have provided hardness verification.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>