A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance

Abstract

An all-MOS, four-quadrant analog multiplier with single-ended voltage output and good temperature performance is presented. It is based on a linear MOS transconductor with extended operation range to four quadrants and on a linear MOS resistor. The temperature behavior of the multiplier is improved by a factor of 10. The multiplier was realized using a 3- mu m p-well self-aligned contact CMOS (SACMOS) process. A linearity better than 1% for each of the input voltages of 5 V/sub p-p/, a bandwidth from DC to 1.2 MHz, and output noise 73 dB below full scale were achieved. The active chip area is 210 mil/sup 2/ and power consumption is 6 mW. A new approach for implementing a temperature-independent analog multiplier is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>