Novel technique for built-in self-test of FPGA interconnects

Abstract

This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding. The proposed scheme requires a total of six test configurations and has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.