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A quantitative analysis of stress induced excess current (SIEC) in SiO/sub 2/ films
42
Citations
10
References
1996
Year
Unknown Venue
EngineeringSilicon On InsulatorSemiconductor DeviceTunneling MicroscopyNanoelectronicsQuantitative AnalysisLow-level StressElectron TunnelingSio/sub 2/Thin Film ProcessingMaterials ScienceElectrical EngineeringPhysicsSemiconductor Device FabricationNeutral TrapMicroelectronicsStress-induced Leakage CurrentApplied PhysicsThin FilmsElectrical Insulation
The low-level stress induced excess current (SIEC) characteristics of 92 /spl Aring/ wet oxide are investigated in detail. As a result of the systematic investigations of the low-level E-J characteristics and the corresponding changes of net oxide charge, we have found that SIEC can be interpreted as electron tunneling processes into five kinds of different traps. As for the reproducible SIEC components, a quantitative analysis has been developed. By precisely modeling the trap assisted tunneling process, it has been shown that the E-J and t-J characteristics of the pretunneling region can be completely simulated as an electron tunneling process into the neutral trap. Using this analysis, it has been found that the local neutral trap density in bulk SiO/sub 2/ remains constant under the same hole fluence Qhole, regardless of the electric field strength during V/sub g/>0 FN stresses. In consequence, it has been concluded that the neutral trap has been created by holes injected into the oxide during the stresses.
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