Modeling and Parameter Extraction for the Series Resistance in Thin-Film Transistors

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A new parameter extraction method is proposed for the series resistance of thin-film transistors (TFTs). By analyzing the gate–source overlap region of staggered structure TFTs, the model for the series resistance is derived and utilized for the parameter extraction. To verify the extraction method, the characteristics of amorphous silicon TFTs obtained from TCAD simulation are used. For the devices with different overlap lengths, the extracted parameters are identical to each other, although the series resistances are different due to the narrow overlap length. When the actual channel length is different from the mask-specified length, the offset length can be effectively corrected by the new method, so that accurate parameters can be obtained. Because the new method has several advantages such as the accuracy and generality over the conventional method, it can be used for further analysis of TFT characteristics. </para>