On-chip current sensing circuit for CMOS VLSI

Abstract

CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8*8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>