Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

Abstract

In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: (1) ultralow <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> (more than three decades lower than in the case of a device on uniformly strained silicon); (2) boosting of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> (more than one decade higher compared to a silicon reference); and (3) an average subthreshold swing <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the tunnel FET, which could be a disadvantage for logic design with tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side.