Proceedings of the International Conference on Parallel Processing · 1993 · 14 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingReconfigurable ComputingField-programmable Gate Array ArchitectureInterconnect ArchitectureParallel ArchitecturesParallel Computer ArchitectureReconfigurable System ArchitectureRouting ArchitecturePropagation Delay ModelingReconfigurable Array ArchitectureReconfigurable ArraysReconfigurable MicroarchitectureReconfigurable Processor ArchitecturesRouting For Reconfigurable SystemsSignal PropagationSignal Propagation Delay
Massively parallel computers are implemented by means of modules at different packaging levels. This paper discusses a hierarchical node clustering scheme (HNC) for packaging a class of reconfigurable processor arrays called Polymorphic Processor Array (PPA) which uses circuit-switching- based routers at each node to deliver a different topology at every instruction. The PPA family suffers from an unknown signal delay between arbitrary two nodes connected by the circuited-switched paths. This either forces the hardware clock to compromise to the worst signal delay or makes the software dependent on the system size. The use of the HNC scheme allows to obtain communication speed-up and automatic control, at the compiler level, over signal propagation delay.
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