High speed redundant self-correcting circuits for radiation hardened by design logic

Abstract

Self-correcting fine-grained triple redundant circuits using majority gate feedback for single event upset and transient radiation hardening are described and compared to other hardening approaches. The approach votes the triple modular redundant (TMR) state in the state element feedback path, which allows high performance commensurate with commercial integrated circuits. Clock gating is supported. The TMR self-correcting approach is used in a built-in self-test engine to evaluate a 16 k-byte cache design. The circuits have been fabricated on a 90 nm low standby power bulk CMOS process. Data paths have been tested at clock frequencies up to 500 MHz. TID tests using Co-60 indicate negligible standby current increase at over 2 Mrad(Si) and ion tests show SEE hardness beyond 100 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg LET.