Design considerations for a high-performance 3-μm CMOS analog standard-cell library

Abstract

Several design aspects of a high-performance analog cell library implemented in 3-/spl mu/m CMOS are described, including an improved central biasing scheme, a circuit for high-swing cascode biasing, an impact ionization shielding technique, and a family of operational transconductance amplifiers including a precision low offset-voltage amplifier utilizing lateral bipolar transistors.