Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering

TLDR

The study investigates scaling challenges of a vertical tunnel field‑effect transistor. The authors employ a gated silicon p‑i‑n diode with gate‑controlled band‑to‑band tunneling and use gate work‑function engineering to optimize on‑ and off‑currents. The device exhibits exponentially rising input characteristics, perfect output saturation, and sub‑100‑nm channel lengths achieve off‑currents around 1 fA/µm²; adding a Δp⁺ SiGe layer improves on‑current, threshold voltage, and subthreshold swing while slightly raising off‑currents, yet overall performance remains largely independent of channel length and oxide thickness, making it suitable for low‑power analog applications.

Abstract

In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.