A 65-nm CMOS ultra-low-power LC quadrature VCO

Abstract

An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ¿W at a 0.6V supply. At this supply the simulated tuning range and phase noise at 1 MHz offset are 10.4% (2.34-2.59 GHz) and -113.4 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 187 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.