Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

Abstract

This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart power applications. These high drain voltages potentially make N-LDMOS hot carrier degradation an important reliability concern. This paper focuses on the hot carrier test methodology and geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it describes for the first time the HC performance of N-LDMOS transistor arrays rather than discrete devices and discusses an N-LDMOS failure mode not yet addressed in the literature.