2002 · 10 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringDigital CommunicationLow-power DesignMicroelectronicsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDigital Integrated CircuitsIntegrated Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationCmos Analog Integrated CircuitsEthernetGigabit EthernetLow-voltage Cmos DesignNetwork Interface DesignRobust PerformanceTransceiver ArchitecturesTransceiver Design
This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 /spl mu/m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm/sup 2/ and consumes 350 mW of power.
3
A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet
J. Everitt, James F. Parker, P.J. Hurst et al. · IEEE Journal of Solid-State Circuits · 1998 · 28 citations
Engineering, Computer Engineering, Electrical Engineering +17