Design Technique of an On-Chip, High-Voltage Charge Pump in SOI

Abstract

A design methodology for an on-chip charge pump that utilizes SOI CMOS charge transfer switches is presented. The limiting factors of a bulk CMOS process to produce a high-voltage, on-chip converter are outlined. The power efficiency has been improved due to low stray capacitance inherent in the SOI process. The circuit has been simplified from the conventional charge pump for implementation in an SOI process, which saves active chip area. A 9-stage charge pump is designed to produce a 27 V output from a 3.3 V supply. The design was fabricated in a 0.35 /spl mu/m SOI CMOS process. A power efficiency of 91% is achieved at a load current of approximately 40 /spl mu/A.