LINEARITY IMPROVEMENT OF CASCODE CMOS LNA USING A DIODE CONNECTED NMOS TRANSISTOR WITH A PARALLEL RC CIRCUIT

Abstract

A fully integrated 5.5GHz high-linearity low noise amplifler (LNA) using post-linearization technique, implemented in a 0.18m RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise flgure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8:33dBm, a power gain of 10.02dB, and a NF of 3.05dB at 5.5GHz biased at 6mA from a 1.8V power supply.