A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Abstract

This paper proposes three circuit technologies for achieving mega-bit-class nonvolatile ferroelectric RAMs (NVFRAMs). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAMs. Problems and countermeasures in introducing this scheme into NVFRAMs are also discussed. A proposed optimized C/sub B//C/sub S/ cell array design method provides a relationship between bit line capacitance C/sub B/ and memory cell capacitance C/sub S/, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-/spl mu/m CMOS process. This chip has an access time of 60 ns and a die size of 15.7/spl times/5.79 mm/sup 2/.