Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data

Abstract

The RC delay of an interconnect is a critical parameter that does not improve with process scaling, but rather increases. Interconnect delay considerably degrades the performance of today's sophisticated microprocessors, so much work has been done to reduce both this delay and its influence on performance . In a chip multiprocessor, process scaling would improve the intrinsic speed of each processor tile, but overall chip speed would not increase because of the limits to communication between tiles. The communication performance is limited by not only RC-delay increase but also arising network congestion and contention. Regarding the latter, effective use is made of network techniques developed in both interconnection networks for off-chip multiprocessors and communication networks for packet switching. This elastic interconnect for internal communications on-chip multiprocessors is a fundamental technique capable of enhancing conventional network techniques by effectively utilizing on-chip repeater-inserted long wiring.