Device Technology for Body Biasing Scheme

Abstract

We report power-aware 65-nm node CMOS device technology suitable for a body biasing scheme. For high-performance CMOS, both channel and halo profiles have been optimized to enhance the body-bias effect of 45-nm gate length devices. Standby leakage reduction without device reliability compromise has been demonstrated with simultaneous voltage control of the body bias and power supply. Moreover, high-k gate dielectric "HfSiON" has been adopted to reduce both gate leakage and GIDL, which are the dominant standby leakage components of low standby power CMOS.