A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applications

Abstract

An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.