IEEE Transactions on Computers · 2007 · 56 citations · 27 references
EngineeringComputer EngineeringComputer SystemsFault ToleranceFault-tolerant ComputingReconfigurable ComputingBuilt-in Self-testConfigurable Logic BlocksDesign For TestabilityPartial ReconfigurationReconfigurable System ArchitectureArea Overhead AnalysisDesign For ScanabilityFlip-flopsLow-power Test DesignScan Chain DesignScan DesignScan StrategyTesting Cost
A new scan architecture called reconfigured scan forest is proposed for cost-effective scan testing. Multiple scan flip-flops can be grouped based on structural analysis that avoids new untestable faults due to new reconvergent fanouts. The proposed new scan architecture allows only a few scan flip-flops to be connected to the XOR trees. The size of the XOR trees can be greatly reduced compared with the original scan forest; therefore, area overhead and routing complexity can be greatly reduced. It is shown that test application cost, test data volume, and test power with the proposed scan forest architecture can be greatly reduced compared with the conventional full scan design with a single scan chain and several recent scan testing methods
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Reducing test application time for full scan embedded cores
İlker Hamzaoğlu, J.H. Patel · 2003 · 337 citations
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations