Concepedia

Publication | Closed Access

Dynamic thread assignment on heterogeneous multiprocessor architectures

242

Citations

14

References

2006

Year

TLDR

Heterogeneous chip multiprocessors, comprising cores and caches of varying size and complexity, better accommodate multi‑programmed workloads where threads differ in runtime characteristics and resource demands. The study proposes a dynamic thread‑assignment policy that observes running thread behavior and migrates them across cores to improve performance. The policy is evaluated via simulation using a mix of Alpha EV5 and EV6 processors running integer and floating‑point SPEC2000 benchmark programs. Results show that dynamic assignment outperforms static allocation by 20–40 % on average and up to 80 % in extreme cases, depending on multithreading level.

Abstract

In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distinct threads differ, but each thread may also present diversity in its performance and resource usage over time. A heterogeneous chip multiprocessor (CMP) architecture consists of processor cores and caches of varying size and complexity. Prior work has shown that heterogeneous CMPs can meet the needs of a multi-programmed computing environment better than a homogeneous CMP system. In fact, the use of a combination of cores with different caches and instruction issue widths better accommodates threads with different computational requirements.A central issue in the design and use of heterogeneous systems is to determine an assignment of tasks to processors which better exploits the hardware resources in order to improve performance. In this paper we argue that the benefits of heterogeneous CMPs are bolstered by the usage of a dynamic assignment policy, i.e., a runtime mechanism which observes the behavior of the running threads and exploits thread migration between the cores. We validate our analysis by means of simulation. Specifically, our model assumes a combination of Alpha EV5 and Alpha EV6 processors and of integer and floating point programs from the SPEC2000 benchmark suite. We show that a dynamic assignment can outperform a static one by 20% to 40% on average and by as much as 80% in extreme cases, depending on the degree of multithreading simulated.

References

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