A 6-bit 5-GSample/s Nyquist A/D converter in 65nm CMOS

Abstract

A 6-bit Nyquist A/D converter (ADC) that converts at 5 GHz is reported. Using a wideband track-and-hold amplifier, array averaging, reset switches on analog signal paths, and phase-adjusted clocking for cascaded comparators, a 6-bit flash ADC achieves better than 5 effective bits for input frequencies up to 2.5 GHz at 5 GSample/s. This ADC does not rely on time interleaving, digital calibration, and post data processing for its dynamic performance. Peak INL and DNL are less than 0.7 LSB and 0.6 LSB, respectively. This ADC consumes about 320 mW from 1.3 V at 5 GSample/s. The chip occupies 0.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, fabricated in 65 nm CMOS.