2014 · 64 citations · 9 references
EngineeringComputer EngineeringDesign OptimizationLow-power DesignSystem-on-chip DesignDevice ScalingIntegrated Circuit DesignInterconnect ArchitectureInterconnect DesignPower-aware DesignVery-large-scale Integration Layout3D Integrated CircuitsFloorplanningIntegrated Circuit FloorplanningInterconnect FloorplanningThermal-aware LayoutThermal-aware Physical DesignThree-dimensional Integrated Circuit LayoutTungsten Interconnects
In this paper we study the power vs. performance tradeoff in block-level monolithic 3D IC designs. Our study shows that we can close the power-performance gap between 2D and a theoretical lower bound by up to 50%. We model the inter-tier performance variations caused by a low temperature manufacturing process on the non-bottom tiers. We also model an alternate manufacturing process, where highly resistive tungsten interconnects are used on the bottom tier to withstand a high temperature process on the non-bottom tiers. We propose a variation-aware floorplanning technique that makes our design more tolerant to these variations. We demonstrate that our design methods can help us obtain high quality designs even under inter-tier performance variations.
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