IEEE Transactions on Consumer Electronics · 2011 · 68 citations · 22 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDigital CommunicationLow-power DesignDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureLow-power Digital Circuit DesignLow-power Fpga DesignPower OptimizationInverse Fourier TransformMultiplier DesignMultipliersOrthogonal Frequency-division MultiplexingPower ConsumptionRead-only MemoryReconfigurable Hardware ArchitectureWireless Communication Systems
4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.
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An algorithm for the machine calculation of complex Fourier series
J.W. Cooley, John W. Tukey · Mathematics of Computation · 1965 · 12.2K citations
Pierre Duhamel, Henk D. L. Hollmann · Electronics Letters · 1984 · 421 citations