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Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors
207
Citations
19
References
2009
Year
Materials ScienceElectrical EngineeringConstant-voltage-bias Stress TestingSub XmlnsEngineeringCrystalline DefectsStress-induced Leakage CurrentBias Temperature InstabilityApplied PhysicsChannel LayersSemiconductor MaterialIgzo TftsThin Film Process TechnologyThin FilmsThin Film ProcessingSemiconductor Device
Constant-voltage-bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 30 V) stress measurements are performed for a period of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs tested exhibit the following: 1) a positive rigid log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> )-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> / IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.
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