An efficient inductance modeling for on-chip interconnects

Abstract

In this paper, we present an efficient yet accurate inductance extraction methodology. We first show that without loss of accuracy, the extraction problem of n traces can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a table-based approach. The table-based inductance model has been integrated with a statistically-based RC model generation to generate RLC models for on-chip interconnects. Application examples show that our method is efficient enough to be used during iterative procedures of interconnect simulation and layout optimization.