$W$-Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS

TLDR

The paper develops low‑noise W‑band amplifiers and milliwatt‑level 170–200 GHz output doublers in 45‑nm SOI CMOS. The authors model transistors with R/C extraction and full electromagnetic simulation and implement a three‑stage W‑band amplifier and balanced doubler in 45‑nm SOI CMOS. Measured results show a record 6.0‑dB noise figure, 7.5–8.0 dBm saturated output, 9 % PA efficiency at 95 GHz, and milliwatt‑level output (≈1 mW) at 170–200 GHz, demonstrating state‑of‑the‑art performance.

Abstract

This paper presents low-noise -band amplifiers and milliwatt-level 170-200-GHz output doublers in 45-nm semiconductor-on-insulator (SOI) CMOS technology. The transistors are modeled using R/C extraction and full electromagnetic modeling. The measured of a 30 1- transistor is 200-210 GHz at a bias current of 0.3-0.5 . A three-stage -band amplifier shows a record noise figure of 6.0 dB and a saturated output power of 7.5-8.0 dBm with a power-added efficiency of 9%, all at 95 GHz. The -band balanced doubler results in an output power of 1 mW at 180 GHz. A -band amplifier/ -band doubler chip is also demonstrated, with a peak output power of 0.5-1 mW at 170-195 GHz and a conversion gain from to . This paper shows that 45-nm SOI CMOS, built for digital and mixed-signal applications, results in state-of-the-art performance at - and -band.