Computer · 1995 · 158 citations · 8 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsField-programmable Gate ArraysField-programmable Gate Array ArchitectureFpga ArchitectureInterprocess CommunicationRapid PrototypingReconfigurable System ArchitectureDesign PrototypingEmbedded Systems PrototypingField-programmable Gate Arrays (Fpgas)Hardware SchedulingMultiprocessor SchedulingPrototypingPrototyping With Field-programmable Gate ArraysRouting In Field-programmable Gate Arrays
We propose a rapid-prototyping setup to minimize development cost and a structured-prototyping methodology to reduce programming effort. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and field-programmable gate arrays (FPGAs) linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project. Our Graphical Rapid Prototyping Environment (Grape-II) automates the prototyping methodology for these hardware systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. Grape-II has been used successfully in three real-world DSP applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A preliminary architecture for a basic data-flow processor
Jack B. Dennis, David P. Misunas · 1998 · 372 citations · Full text
Buffer memory requirements in DSP applications
M. Adé, Rudy Lauwereins, J.A. Peperstraete · 2002 · 33 citations