A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits

Abstract

A new transistor-level layout generation strategy is presented in this paper. This strategy makes possible to design static CMOS cells for any logic function on demand, allowing a logic minimization without any logic constraints. Results show that this new full automatic transistor-level layout generation methodology is very promising. Thus, the strategy aims at reducing the number of transistors targeting less static consumption and performing transistor sizing to improve circuit performance.