Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Abstract

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V/sub cc/), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V/sub cc/ DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V/sub cc/ of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3- mu m electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>