IEEE Transactions on Circuits & Systems II Express Briefs · 2010 · 16 citations · 10 references
EngineeringElectrical EngineeringAnalog ElectronicsDigital CommunicationMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-noise Circuit DesignNoise In Analog CircuitsAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Integrated CircuitsDigital-to-analog Converter DesignDigital-to-analog ConvertersFeedbackModulator Design
A new ΣΔ modulator architecture that shapes digital-to-analog converter (DAC) mismatches in a manner similar to quantization noise shaping is proposed, allowing operation with low oversampling ratios, high-resolution quantizers, and compact logic. It is shown that the proposed architecture entails a smaller feedback logic delay than data-weighted-averaging techniques, providing a fourfold delay reduction for a 6-bit feedback DAC. The front-end integrator implementation also exhibits 25% less kT/C noise than conventional architectures.
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