R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip

Abstract

A coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented. Review of on-chip wiring guidelines with respect to the inaccuracies of an RC coupling evaluation for known net topologies is discussed in terms of tool requirements for full-chip noise evaluation which include inductive coupling effects. The extraction and simulation approach is described in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full chip noise evaluation. Results are presented which compare noise amplitude differences between RC and R(f)L(f)C evaluations for the wiring data of an S/390 microprocessor as well as pertinent statistics such as run times and memory usage.