Background digital calibration techniques for pipelined ADCs

TLDR

The technique applies to capacitor‑ratioed MDACs used in multistep or pipelined ADCs. The study develops a skip‑and‑fill algorithm for real‑time digital self‑calibration of pipelined ADCs. It skips random conversion cycles, injects a calibration test signal via split‑reference injection, and reconstructs missing data with a 44th‑order polynomial interpolation, achieving 16‑bit accuracy over two‑thirds of the Nyquist bandwidth. The method replaces factory trimming, enables digital calibration hardware, simplifies self‑calibration, and improves performance while keeping the system architecture simple.

Abstract

A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDACs) commonly used in multistep or pipelined ADCs. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multistep or pipelined ADCs. The proposed method improves the performance of the inherently fast ADCs by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, of amp DC gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within two-thirds of the Nyquist bandwidth is recovered with 16-b accuracy using a forty-fourth order polynomial interpolation, behaving essentially as an FIR filter,.