Software-Based Self-Testing of Embedded Processors

TLDR

Software‑based self‑testing of embedded processors offers at‑speed, nonintrusive testing without hardware or performance overhead, presenting a promising alternative to traditional external testers and hardware BIST. The paper proposes a high‑level, functional component‑oriented software‑based self‑testing methodology for embedded processors that targets high structural fault coverage while keeping test development and application costs low. The methodology is implemented as a high‑level, functional component‑oriented software test and validated against existing structural software‑based self‑testing approaches using automatic test pattern generation and pseudorandom testing. Applying the methodology to two different RISC processor implementations, including gate‑level models, demonstrates its effectiveness and efficiency.

Abstract

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.