2002 · 108 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesParallel ArchitecturesReconfigurable System ArchitectureConfigurable Logic Block DesignDensityField-programmable Gate Arrays (Fpgas)Lookup Table ArchitecturesLookup Table DesignProgrammable ArchitectureReconfigurable Computing ArchitecturesReconfigurable Logic Blocks
Reconfigurable field-programmable gate arrays (FPGAs) provide an effective programmable resource for implementing hardware-based artificial neural networks (ANNs). They are low cost, readily available and reconfigurable-all important advantages for ANN applications. However, FPGAs lack the circuit density necessary to implement large parallel ANNs with many thousands of synapses. This paper presents an architecture that makes it feasible to implement large ANNs with FPGAs. The architecture combines stochastic computation techniques with a novel lookup-table-based architecture that fully exploits the lookup-table structure of many FPGAs. This lookup-table-based architecture is extremely efficient: it is capable of supporting up to two synapses per configurable logic block (CLB). In addition, the architecture is simple to implement, self-contained (weights are stored directly in the synapse), and scales easily across multiple chips.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Device for generating binary sequences for stochastic computing
M. van Daalen, Peter Jeavons, John Shawe‐Taylor et al. · Electronics Letters · 1993 · 42 citations