Logical verification of the NVAX CPU chip design

Abstract

The NVAX CPU chip is a highly complex VAX microprocessor that required a rigorous verification effort to ensure that there were no logical errors in the design. A simulation-based verification strategy using several different models and simulators was used. At the core of the verification effort were implementation-oriented, directed, pseudorandom exercisers. These exercisers were supplemented with implementation-specific focused tests and already existing VAX architectural tests. An extensive amount of simulation was performed on a schematics-derived model including the simulation of the VMS operating system boot process. The verification effort was directed by bug detection. Only 15, unobtrusive, logical bugs were found in the first-pass design, and the operating system booted with first-pass chips in a prototype system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>