CrossCheck: a cell based VLSI testability solution

Abstract

A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. The sizable number of test points improves the testability of the designs by a very large factor. Additionally, analog measurement and signal injection capabilities allow detection of practical CMOS fault modes such as opens, shorts, open or closed FET's and even noise margins.