Congestion-aware task mapping in heterogeneous MPSoCs

Abstract

Multiprocessors systems-on-chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis represented by the gap between the silicon technology and the actual SoC design capacity. MPSoCs may employ NoCs to integrate several programmable processors, specialized memories, and other specific IPs in a scalable way. Besides communication infrastructure, another important issue in MPSoCs is task mapping. Dynamic task mapping is needed, since the number of tasks running in the MPSoC may exceed the available resources. Most works in literature present static mapping solutions, not appropriate for this scenario. This paper investigates the performance of mapping algorithms in NoC-based heterogeneous MPSoCs, targeting NoC congestion minimization. The use of the proposed congestion-aware heuristics reduces the NoC channel load, congestion, and packet latency.